STM8S datasheet(330/467 Pages) STMICROELECTRONICS

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Universal asynchronous receiver transmitter (UART)

RM0016

330/467

DocID14587 Rev 14

Single byte communication

Clearing the TXE bit is always performed by a write to the data register.

The TXE bit is set by hardware and it indicates:

•

The data has been moved from TDR to the shift register and the data transmission has

started.

•

The TDR register is empty.

•

The next data can be written in the UART_DR register without overwriting the previous

data.

This flag generates an interrupt if the TIEN bit is set.

When a transmission is taking place, a write instruction to the UART_DR register stores the

data in the TDR register. The data is copied in the shift register at the end of the current

transmission.

When no transmission is taking place, a write instruction to the UART_DR register places

the data directly in the shift register, the data transmission starts, and the TXE bit is

immediately set.

If a frame transmission is complete (after the stop bit) and the TXE bit is set, the TC bit is

set. An interrupt is generated if the TCIEN is set in the UART_CR2 register. After writing the

last data in the UART_DR register, it is mandatory to wait until TC is set to ‘1’ before

entering Halt mode or disabling the UART (see Figure 116: TC/TXE behavior when

transmitting).

The following software sequence is required to clear the TC bit:

Read from the UART_SR register

Write to the UART_DR register

Figure 116. TC/TXE behavior when transmitting

1. This example assumes that several other transmissions occur after TE has been set.

Note:

The TC bit can also be cleared by writing a ‘0’ to it. This clear sequence is recommended

only for multibuffer communication.

TX line

USART_DR

TC flag

because TXE=0

software waits until TC=1

TC is set because

TXE=1

set

Idle preamble

by hardware

software

enables the

USART

TC is not set

because TXE=0

TXE flag

software waits until TXE=1

and writes F1 into DR

software waits until TXE=1

and writes F3 into DR

software waits until TXE=1

and writes F2 into DR

Frame 1

Frame 2

Frame 3

set by hardware

cleared by software

set by hardware

cleared by software

TC is not set

ai17121d

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