STM8S datasheet(339/467 Pages) STMICROELECTRONICS

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RM0016

Universal asynchronous receiver transmitter (UART)

377

22.3.7

Multi-processor communication

It is possible to perform multi-processor communication with the UART (several UARTs

connected in a network). For example, one of the UARTs can be the master, its TX output is

connected to the RX input of the other UART. The others are slaves, their respective TX

outputs are logically ANDed together and connected to the RX input of the master.

In multi-processor configurations it is often desirable that only the intended message

recipient should actively receive the full message contents, thus reducing redundant UART

service overhead for all non addressed receivers.

The non addressed devices may be placed in mute mode by means of the muting function.

In mute mode:

•

None of the reception status bits can be set.

•

All the receive interrupts are inhibited.

•

The RWU bit in UART_CR2 register is set to 1. RWU can be controlled automatically

by hardware or written by the software under certain conditions.

The UART can enter or exit from mute mode using one of two methods, depending on the

WAKE bit in the UART_CR1 register:

•

Idle Line detection if the WAKE bit is reset,

•

Address Mark detection if the WAKE bit is set.

Idle line detection (WAKE = 0)

The UART enters mute mode when the RWU bit is written to 1.

It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but

the IDLE bit is not set in the UART_SR register. RWU can also be written to 0 by software.

An example of mute mode behavior using idle line detection is given in Figure 120.

Figure 120. Mute mode using idle line detection

Address mark detection (WAKE = 1)

In this mode, bytes are recognized as addresses if their MSB is a ‘1’ else they are

considered as data. In an address byte, the address of the targeted receiver is put on the 4

LSB. This 4-bit word is compared by the receiver with its own address which is programmed

in the ADD bits in the UART_CR4 register.

The UART enters mute mode when an address character is received which does not match

its programmed address. The RXNE flag is not set for this address byte and no interrupt

request is issued as the UART would have entered mute mode.

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