STM8S datasheet(382/467 Pages) STMICROELECTRONICS

382 / 467 page

Controller area network (beCAN)

RM0016

382/467

DocID14587 Rev 14

23.4.2

Normal mode

Once the initialization has been done, the software must request the hardware to enter

Normal mode, to synchronize on the CAN bus and start reception and transmission. This

request to enter Normal mode is done by clearing the INRQ bit in the CAN_MCR register.

Afterwards, the beCAN is synchronized with the data transfer on the CAN bus by waiting for

the occurrence of a sequence of 11 consecutive recessive bits (Bus Idle state) before

finishing the switch to Normal mode and being ready to take part in bus activities. The

switch completion is confirmed by hardware by clearing the INAK bit in the CAN_MSR

The initialization of the filter values is independent from Initialization mode but must be done

while the filter bank is not active (corresponding FACTx bit cleared). The filter bank scale

and mode configuration must be configured in initialization mode.

23.4.3

Sleep mode (low power)

To reduce power consumption, beCAN has a low power mode called Sleep mode. This

mode is entered on software request by setting the SLEEP bit in the CAN_MCR register. In

this mode, the beCAN clock is stopped, however software can still access the beCAN

mailboxes.

Note:

If software requests entry to initialization mode by setting the INRQ bit while beCAN is in

sleep mode, it must also clear the SLEEP bit.

beCAN can be woken up (exit Sleep mode) either by software clearing the SLEEP bit or on

detection of CAN bus activity.

On CAN bus activity detection, hardware automatically performs the wakeup sequence by

clearing the SLEEP bit if the AWUM bit in the CAN_MCR register is set. If the AWUM bit is

cleared, software has to clear the SLEEP bit when a wakeup interrupt occurs, in order to exit

from sleep mode.

Note:

If the wakeup interrupt is enabled (WKUIE bit set in CAN_IER register) a wakeup interrupt

will be generated on detection of CAN bus activity, even if the beCAN automatically

performs the wakeup sequence.

After the SLEEP bit has been cleared, Sleep mode is exited once beCAN has synchronized

with the CAN bus, refer to Figure 142: beCAN operating modes. However the Rx line has to

be in recessive state to leave this mode. Sleep mode is exited once the SLAK bit has been

cleared by hardware.

23.4.4

Time triggered communication mode

The TTCM (Time Triggered Communication Mode in CAN_MCR) bit has to be set to enable

the Time Triggered Communication mechanism.

In this mode, the internal counter of the CAN hardware is activated and used to generate the

Time Stamp value stored in the CAN_MTSRH and CAN_MTSRL registers (for Rx and Tx

mailboxes). The internal counter is captured on the sample point of the Start Of Frame bit in

both reception and transmission.

The TGT bit (Transmit Global Time in CAN_MDLCR) enables automatic transmission of the

contents of both CAN_MTSRH and CAN_MTSRL in the two last data bytes of the message

(refer to the TTCAN specification ISO 11898-4).

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