XRT83SL34 datasheet(21/80 Pages) EXAR

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XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.0.8

FUNCTIONAL DESCRIPTION

The XRT83SL34 is a fully integrated four chnnel short-haul transceiver intended for T1, J1 or E1 systems.

Simplified block diagrams of the device are shown in Figure 1, Host mode and Figure 2, Hardware mode.

In T1 applications, the XRT83SL34 can generate five transmit pulse shapes to meet the short-haul Digital

Cross-connect (DSX-1) template requirement. The operation and configuration of the XRT83SL34 can be

controlled through a parallel microprocessor Host interface or Hardware control.

MASTER CLOCK GENERATOR

Using a variety of external clock sources, the on-chip frequency synthesizer generates the T1 (1.544MHz) or

E1 (2.048MHz) master clocks necessary for the transmit pulse shaping and receive clock recovery circuit.

There are two master clock inputs MCLKE1 and MCLKT1. In systems where both T1 and E1 master clocks are

available these clocks can be connected to the respective pins. All channels of a given XRT83SL34 must be

operated at the same clock rate, either T1, E1 or J1 modes.

In systems that have only one master clock source available (E1 or T1), that clock should be connected to both

MCLKE1 and MCLKT1 inputs for proper operation. T1 or E1 master clocks can be generated from 8kHz,

16kHz, 56kHz, 64kHz, 128kHz and 256kHz external clocks under the control of CLKSEL[2:0] inputs according

to Table 1.

NOTE: EQC[4:0] determine the T1/E1 operating mode. See

Table 5 for details.

FIGURE 4. TWO INPUT CLOCK SOURCE

FIGURE 5. ONE INPUT CLOCK SOURCE

MCLKE1

MCLKT1

MCLKOUT

1.544MHz

2.048MHz

+/-50ppm

1.544MHz

+/-50ppm

Two Input C lock Sources

MCLKE1

MCLKT1

MCLK OUT

1.544MHz

2.048MHz

One Input Clock Source

Input Clock Options

8kHz

16kHz

56kHz

64kHz

128kHz

256kHz

1.544MHz

2.048MHz

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