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XRT83SL34 데이터시트(PDF) 59 Page - Exar Corporation |
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XRT83SL34 데이터시트(HTML) 59 Page - Exar Corporation |
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59 / 80 page ![]() XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PRELIMINARY REV. P1.0.8 56 TABLE 26: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION REGISTER ADDRESS 0000111 0010111 0100111 0110111 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 FUNCTION REGISTER TYPE RESET VALUE BIT #NAME D7 Reserved RO 0 D6 Reserved RO 0 D5 CLOS5_n Cable Loss bit 5: CLOS[5:0]_n are the six bit receive selec- tive equalizer setting which is also a binary word that repre- sents the cable attenuation indication within ±1dB. CLOS5_n is the most significant bit (MSB) and CLOS0_n is the least sig- nificant bit (LSB). RO 0 D4 CLOS4_n Cable Loss bit 4: See description of D5 for function of this bit. RO 0 D3 CLOS3_n Cable Loss bit 3: See description of D5 for function of this bit. RO 0 D2 CLOS2_n Cable Loss bit 2: See description of D5 for function of this bit. RO 0 D1 CLOS1_n Cable Loss bit 1: See description of D5 for function of this bit. RO 0 D0 CLOS0_n Cable Loss bit 0: See description of D5 for function of this bit. RO 0 |
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