XRT83SL34 datasheet(80/80 Pages) EXAR

80 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.0.8

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order

to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of

any circuits described herein, conveys no license under any patent or other right, and makes no represen-

tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for

illustration purposes and may vary depending upon a user’s specific application. While the information in

this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where

the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-

tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-

tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury

or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-

ration is adequately protected under the circumstances.

Datasheet February 2004.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

REVISIONS

REV #DESCRIPTION

P1.0.0

Initial Issue.

P1.0.1

Revised definitions for bits D6-Do of tables 27 thru 34. Removed reference to long-haul.

P1.0.2

Modified formatting of data sheet and made various edits to text.

P1.0.3

Corrected Microprocessor Interface timing diagrams and data.

P1.0.4

Definition of TXON_n pin changed. RXON_n bit included in the register maps. Table 4, EQC4 and EQC3

changed. RX transformer changed from 2:1 to 1:1. Removed references to 1:2.42 transformer ratio.

Added detailed explanation of LOS operation. Added description of arbitrary pulse. Added description of

the operation of the TRATIO bit. Included Device ID. Added description of Gap Clock Support.

P1.0.5

Minor edits to block diagram, changed issue date to January, corrected register 67 in table 18, corrected

table 37.

P1.0.6

Swapped the function of µPTS1 and µPTS2. Replaced µProcessor timing diagrams and timing informa-

tion, (Figures 27 and 28 -- Tables 49 and 50).

P1.0.7

Updated the Power Consumption numbers.

P1.0.8

Added the New E1 Arbitrary Pulse Feature. Added descriptions to the global registers.

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