18

17

16

15

14

13

12

11

10

D6

D7

9

8

7

6

5

4

3

2

1

CLK

A–1–A16

(Word-Wide)

E

WR

WE

LBA

D4

D2

D3

D1

D0

OE

BAA

QV

DQ0–DQ7 and

DQ24–DQ31

(Word-Wide)

RY/BY

VDDI/VDDE

RP

D5

A0

BASIC/ENHANCED

PIN SET

DCR0

OE

MODE

DCR1

WE

MODE

DCR2

DIS/WORD

DCR3

LRV/BAA

DCR4

BURST

LENGTH

DCR25,24

BURST

LATENCY (X)

DCR29,28

BURST

LATENCY (Y)

DCR30

x16 WRITE

OPTION

DCR31

Basic pin set (DCR0 = 0)

0

X

1

(see Note D)

1

(see Note E)

01

(see Note F)

11

(see Note G)

0

(see Note G)

X

Enhanced pin set (DCR0 = 1)

0

X

1

(see Note D)

1

(see Note E)

01

(see Note F)

11

(see Note G)

0

(see Note G)

X

NOTES: A. X is a don’t care.

B. See Table 8 through Table 12 for DCR setting descriptions.

C. Linear burst with the enhanced pin set requires LBO = VIL.

D. 5–1– . . . –1 is available only with the 16-bit data bus, which requires DCR3 = 1 and WORD=VIL.

E. For synchronous OE (DCR1 = 0), BAA is not required to burst if required to burst if OE is used to control the burst (DCR[29:28] = 00).

F. 5–1– . . . –1 is available with MOD4, MOD8, MOD16, and MOD32.

G. Linear MOD8 burst is available with 3–1– . . . –1, 4–1– . . . –1, 5–1– . . . –1, and 4–2– ...–2.

Figure 16. 5–1–...–1 MOD8 Linear Burst With Device Configuration Register Settings

ADVANCE INFORMATION