TMS28F033

4194304-BIT

SYNCHRONOUS FLASH MEMORY

SMJS833 – NOVEMBER 1997

13

POST OFFICE BOX 1443

device configuration defaults (continued)

Table 8. Device Configuration Register Bit Definitions and Functions (Continued)

DCR BIT

FUNCTION

DATA

COMMENTS

DCR8 – DCR23

Reserved for Texas

Instruments (TI

™) and

should not be used

0000h

DCR25, DCR24

Burst length

00 = MOD4 (default)

01 = MOD8

10 = MOD16

11 = MOD32

(see Note 6)

There are four available burst length settings. The

MOD4

burst

is

a

modulo

burst

of

four

words/double-words for x16/x32, respectively. The

other available burst lengths are MOD8, MOD16, and

MOD32 (see Table 12).

DCR27, DCR26

Reserved for TI and

should not be used

00 – (default)

(see Note 6)

DCR29, DCR28

Burst latency (X)

00 = OE-controlled (default if in

x32 mode and when OE is

synchronous)

01 = 3 cycles

10 = 4 cycles (default if in x16

mode or when OE is

asynchronous)

11 = 5 cycles

(see Note 6)

The four X latency possibilities are OE-controlled

burst, and 3, 4, or 5 clock cycles for BAA-controlled

burst. X latency denotes the number of clock cycles

required to access the first word from memory (see

Table 10 and Table 11).

DCR30

Burst latency (Y)

0 = 1 cycle (default)

1 = 2 cycles

(see Note 6)

The two Y latency possibilities are one clock cycle and

two clock cycles. Y latency denotes the number of

clock cycles required to access the subsequent words

to complete the cache fill (see Table 10 and Table 11).

DCR31

One- or two-word write

option for x16 mode

0 = Program one word

(two

1 = Program two words

(three-cycle write)

(see Note 6)

Applicable for x16 mode only. When DCR31 = 0, only

one word (16 bits) is programmed in two cycles for

each program command received by the CSM. When

DCR31 = 1, two words (32 bits) are programmed in

three cycles for each program command received by

the CSM (see Table 5).

NOTES:

5. The default setting for these bits is set at the factory prior to shipping.

6. These bits return to the default setting after a power-on reset is performed; therefore, it is necessary to program these bits to the

desired configuration.

control pin functions

The DCR0 bit is the control pin configuration bit that selects between the basic or enhanced pin set (see Table 8

and Table 9). With the enhanced pin set (DCR0 = 1), five additional pins are available: chip enable (E), data valid

(QV), ready/busy (RY/BY), 3.3-V/5-V IO voltage select (3/5IO), and linear burst order (LBO). With the basic pin

of output enable (OE) and write enable (WE), respectively. DCR3 determines the function of pin 78 as either

output disable (DIS) or word enable (WORD) (see the Terminal Functions table). When DCR3 = 0 (for DIS

usage) the device is forced into using the 32-bit data bus (see Figure 21). When DCR3 = 1, both the 16-bit and

32-bit data buses are available. The DCR4 bit determines the function of pin 79 as either low-regulator-voltage

detection (LRV) or burst-address advance (BAA).

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