TMS28F033 datasheet(21/52 Pages) TI

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TMS28F033

4194304-BIT

SYNCHRONOUS FLASH MEMORY

SMJS833 – NOVEMBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

reduced power mode

The command F0h, when written to the CSM, puts TMS28F033 in reduced-power mode (not to be confused

with RP). This mode is used when the chip-enable, E, input is not used and reduced power consumption is

needed. However, the device does not have its outputs disabled; instead, it can respond to any CSM command

at any time and then its power comes back up. When in reduced power mode, the outputs are still OE-controlled.

RP input (reset/deep power-down mode)

When RP is high, the memory functions normally. When RP goes low, any CSM activity is terminated

immediately. While RP is low, the memory does not respond to read requests and does not accept write

commands. When RP goes high, the memory is reinitialized and prepared for normal operation (read mode),

and sets/clears OBEB based on VPP (see Table 3).

low-power-program mode

Low-power-program mode is activated by entering the command code 60h. The low-power-programming mode

enable/disable is a single-cycle command that toggles the state of the LPM bit in the status register. Depending

on the LPM status register bit (see Table 7), the WSM programs by bytes (low-power mode) or by words (normal

mode) (see Table 5 for CSM command).

low regulator voltage (LRV)

LRV is selected for use by setting DCR4 = 0. This signal can be generated by an external power supply monitor

and should go low when VPP is out of regulation (VPP ≤ VPPH). The WSM periodically samples the LRV input

during erasing and programming. When LRV goes low, the status register SB4 is set, providing a more accurate

monitor of VPP than the VPP status bit (SB3).

pipelining

This device supports efficient bus usage by latching the address on the first clock cycle of a read operation, and

then delaying the data phase (delay bringing OE low), thereby allowing the address and data buses to be used

by other parts of the system.

overlapping data and address phases

The address and data phases of consecutive synchronous read or write operations can be overlapped by one

or more clock cycles. This is done by bringing LBA low to latch a new address before the completion of the data

phase of the current cycle. For overlapping synchronous single reads, and overlapping synchronous single

reads with writes, see Figure 27. For overlapping burst reads, see Note C in Figure 14 and Figure 15. For

overlapping synchronous write cycles, see Figure 24.

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