TMS28F033 datasheet(22/52 Pages) TI

22 / 52 page

TMS28F033

4194304-BIT

SYNCHRONOUS FLASH MEMORY

SMJS833 – NOVEMBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

BUS

OPERATION

COMMAND

COMMENTS

Write

Write program

setup

Data = 40h for main array or 04h

for overlay block

Addr = 00000h for synchronous

WE or XXXXXh for

asynchronous WE

Write

Data = Word to be programmed

Addr = Address of word to be

programmed

Read

Status-register data. Status register is

updated on each rising clock.

Wait

Check SB7

1 = Ready, 0 = Busy

Repeat for subsequent words.

Write read-array command after the last word-program operation to

reset the device to read-array mode.

BUS

OPERATION

COMMAND

COMMENTS

Wait

Check SB3

Detect VPP low

(see Note C)

Wait

Check SB4

Detect LRV low

(see Note D)

Wait

Check SB5

Word-program error

(see Note D)

NOTES: A. In this flowchart, the use of “word” refers to both 16-bit and 32-bit data-bus widths.

B. Full status-register check can be done after each word or after a sequence of words.

C. SB3 must be cleared before attempting additional program / erase operations.

D. SB4 and SB5 are cleared only by the clear-status-register command, but this does not prevent additional program operation

attempts.

Figure 4. Automated Programming Flowchart (DCR4 = 0)

Start

Issue Program-Setup

Command and Address

Issue Word Data and

Address

Read Status-Register Bits

SB7 = 1

Yes

Full Status-Register Check

(optional)

Read Status-Register Bits

SB3 = 0

VPP Range Error

Word-Program Failed

Yes

Word-Program Passed

SB5 = 0

FULL STATUS-REGISTER-CHECK FLOW

See Note B

Word-Program Completed

SB4 = 0

LRV Detected

Yes

See Note A

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