UPD17P136ACT datasheet(52/292 Pages) NEC

52 / 292 page

CHAPTER 5 DATA MEMORY (RAM)

5.1.3 General Register (GR)

The general register consists of 16 nibbles specified by an arbitrary row address in an arbitrary bank in data memory.

This arbitrary row address in an arbitrary bank is specified by the register pointer (RP) in the system register

(SYSREG).

Figure 5-4 shows the configuration of the general register (GR).

Figure 5-4. General Register (GR) Configuration

5.1.4 Port Registers

A port register consists of eight nibbles allocated at addresses 70H to 73H in each bank of the data memory.

As shown in Figure 5-5, the high-order 3 bits of address 71H of BANK1 and all of addresses 72H and 73H of BANK1

are always set to 0.

Figure 5-5 shows the configuration of the port registers.

Figure 5-5. Port Register Configuration

Port register

Address

70H

P0A

71H

P0B

72H

P0C

73H

P0D

BANK0

P1A

P1B

BANK1

Fixed to “0”

SYSREG

Port register

SYSREG

Port register

Unmounted

0123456789

Column address

BANK0

BANK1

General register

The same register is allocated

for each bank.

Area specifiable as general register

Pointed to by general register

pointer (RP) in system register.

Note that row addresses 0 to 6

of BANK1 are unmounted mem-

ory locations. The register

pointer (RP) should therefore

not specify a row address in this

area.

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