AD9546SLASHPCBZ datasheet(204/205 Pages) AD

204 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 204 of 205

Table 116. Write Byte Format

Slave

address

RAM address high byte

RAM address low byte

RAM

Data 0

RAM

Data 1

RAM

Data 2

Table 117. Send Byte Format

Slave address

RAM address high byte

RAM address low byte

Table 118. Receive Byte Format

Slave address

RAM Data 0

RAM Data 1

RAM Data 2

Table 119. Read Byte Format

Slave

address

RAM address

high byte

RAM address

low byte

Slave

address

RAM

Data 0

RAM

Data 1

RAM

Data 2

I²C Serial Port Timing

SDA

SCL

tSP

tHD; STA

tSU; STA

tSU; DAT

tHD; DAT

tHD; STA

tSU; STO

tBUF

tHIGH

tLOW

Figure 146. I²C Serial Port Timing

Table 120. I2C Timing Definitions

Parameter

Description

tBUF

Bus free time between stop and start conditions

tHD; STA

Repeated hold time start condition

tSU; STA

Repeated start condition setup time

tSU; STO

Stop condition setup time

tHD; DAT

Data hold time

tSU; DAT

Data setup time

tLOW

SCL clock low period

tHIGH

SCL clock high period

Minimum/maximum receive SCL and SDA rise time

Minimum/maximum receive SCL and SDA fall time

tSP

Pulse width of voltage spikes that must be suppressed by the input filter

AD9546/PCBZ 데이터시트(PDF) 204 Page - Analog Devices

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