PRT2011CVL5A datasheet(49/112 Pages) NXP

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Electrical Characteristics

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 08/2020

NXP Semiconductors

NOTE

Timing shown is based on the memory generating read data and read strobe

on the SCK rising edge. The FlexSPI controller samples read data on the

DQS falling edge.

Figure 21. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A2)

NOTE

Timing shown is based on the memory generating read data on the SCK

falling edge and read strobe on the SCK rising edge. The FlexSPI controller

samples read data on a half cycle delayed DQS falling edge.

4.5.2.1.3

DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

Table 40. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A2)

Symbol

Parameter

Value

Unit

Min

Max

Frequency of operation

—

166

MHz

TSCKD

Time from SCK to data valid

—

TSCKDQS

Time from SCK to DQS

—

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-2

Table 41. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

MHz

TIS

Setup time for incoming data

8.67

—

TIH

Hold time for incoming data

—

TSCKDQS

TSCKD

SCK

SIO[0:7]

DQS

Internal Sample Clock

TSCKDQS

TSCKD

TSCKDQS

TSCKD

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