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PRT2011CVL5A 데이터시트(PDF) 54 Page - NXP Semiconductors |
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PRT2011CVL5A 데이터시트(HTML) 54 Page - NXP Semiconductors |
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54 / 112 page ![]() i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 08/2020 54 NXP Semiconductors Electrical Characteristics Figure 28. CSI Gated clock mode—sensor data at rising edge, latch data at falling edge Table 47. CSI gated clock mode timing parameters ID Parameter Symbol Min. Max. Units P1 CSI_VSYNC to CSI_HSYNC time tV2H 33.5 — ns P2 CSI_HSYNC setup time tHsu 1 — ns P3 CSI DATA setup time tDsu 1 — ns P4 CSI DATA hold time tDh 1 — ns P5 CSI pixel clock high time tCLKh 3.75 — ns P6 CSI pixel clock low time tCLKl 3.75 — ns P7 CSI pixel clock frequency fCLK — 80 MHz CSI_PIXCLK CSI_VSYNC CSI_DATA[23:00] P6 P1 P3 P4 CSI_HSYNC P2 P5 P7 |
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