PRT2011CVL5A datasheet(8/112 Pages) NXP

8 / 112 page

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 08/2020

NXP Semiconductors

Architectural Overview

The following subsections provide an architectural overview of the i.MX RT1064 processor system.

2.1

Block diagram

Figure 2 shows the functional modules in the i.MX RT1064 processor system.

Figure 2. i.MX RT1064 system block diagram

Internal Memory

512 KB SRAM

128 KB ROM

Multimedia

Connectivity

eMMC 4.5 / SD 3.0 x2

8 x 8 Keypad

External Memory

I2C x4

UART x8

S/PDIF Tx / Rx

GPIO

SPI x4

ADC

System Control

Secure JTAG

PLL / OSC

RTC and Reset

Enhanced DMA

IOMUX

GP Timer x6

CPU Platform

Arm Cortex-M7

32 KB I-cache

32 KB D-cache

FPU

Dual-channel QuadSPI

External Memory Controller

8-bit / 16-bit SDRAM

Parallel NOR FLASH

NAND FLASH

PSRAM

MPU

NVIC

512 KB TCM/OCRAM

FlexCAN x2 + FlexCAN ( with

USB 2.0 OTG with PHY x2

10 / 100 ENET x2

with IEEE 1588

ADC x2 (16-Channel)

ACMP x4

8 / 16 / 24-bit Parallel CSI

24-bit Parallel LCD

Arm Cortex-M7

32 KB I-cache

32 KB D-cache

FPU

MPU

NVIC

512 KB TCM/OCRAM

PXP

2D Graphics Acceleration

Resize, CSC, Overlay, Rotation

Quadrature ENC x4

QuadTimer x4

FlexPWM x4

Watch Dog x4

Power Management

DCDC

LDO

Temp Monitor

Security

Ciphers and RNG

Secure RTC

eFuse

HAB

I2S / SAI x3

Octal/Hyper Flash/RAM x1

FlexIO x2

HS_GPIO

FlexIO

XBAR/AOI

Flexible Data-Rate supported)

4 MB Flash

20-Channel in total

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