PRT2011CVL5A datasheet(59/112 Pages) NXP

59 / 112 page

Electrical Characteristics

i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 08/2020

NXP Semiconductors

Figure 33. SPDIF_SR_CLK timing diagram

Figure 34. SPDIF_ST_CLK timing diagram

4.8

Analog

The following sections provide information about analog interfaces.

4.8.1

DCDC

Table 53 introduces the DCDC electrical specifications.

SPDIF_SR_CLK high period

srckph

16.0

—

SPDIF_SR_CLK low period

srckpl

16.0

—

Modulating Tx clock (SPDIF_ST_CLK) period

stclkp

40.0

—

SPDIF_ST_CLK high period

stclkph

16.0

—

SPDIF_ST_CLK low period

stclkpl

16.0

—

Table 53. DCDC electrical specifications

Mode

Buck mode, one output

Notes

Input voltage

3.3 V

Min = 2.8 V, Max = 3.6 V

Output voltage

1.1 V

Configurable 0.8 - 1.575 with 25 mV one step

in Run mode

Max loading

500 mA

—

Loading in low power modes

200

A ~ 30 mA

—

Table 52. SPDIF timing parameters (continued)

Characteristics

Symbol

Timing Parameter Range

Unit

Min

Max

SPDIF_SR_CLK

(Output)

srckp

srckph

srckpl

SPDIF_ST_CLK

(Input)

stclkp

stclkph

stclkpl

PRT2011CVL5A 데이터시트(PDF) 59 Page - NXP Semiconductors

PRT2011CVL5A 데이터시트(HTML) 59 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL