 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
STM32H723VG 데이터시트(PDF) 143 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32H723VG 데이터시트(HTML) 143 Page - STMicroelectronics |
|
|
143 / 227 page  DS13313 Rev 2 143/227 STM32H723xE/G Electrical characteristics 208 Table 68. Synchronous non-multiplexed PSRAM write timings(1) 1. Guaranteed by characterization results. Symbol Parameter Min Max Unit t(CLK) FMC_CLK period 2Tfmc_ker_ck –0.5 - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 3 t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck+1.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low 1.62 V <VDD < 3.6 V - 5.5 2.7 V <VDD < 3.6 V 2 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1.62 V <VDD < 3.6 V 1 - 2.7 V <VDD < 3.6 V - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2.5 td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck+1 - td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck+0.5 - tsu(NWAIT- CLKH) FMC_NWAIT valid before FMC_CLK high 3 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 - |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
