STM32H723VG datasheet(166/227 Pages) STMICROELECTRONICS

166 / 227 page

Electrical characteristics

STM32H723xE/G

166/227

DS13313 Rev 2

CADC

Internal

sample and

hold

capacitor

tADCV

REG_

STUP

ADC LDO

startup time

µs

tSTAB

ADC power-

up time

LDO already started

con-

version

cycle

tOFF_

CAL

Offset

calibration

time

135

1/fADC

tLATR

Trigger

conversion

latency for

regular and

injected

channels

without

aborting the

conversion

CKMODE = 00

1.5

2.5

CKMODE = 01

2.5

CKMODE = 10

2.5

CKMODE = 11

2.25

tLATR

INJ

Trigger

conversion

latency for

regular and

injected

channels

when a

regular

conversion

is aborted

CKMODE = 00

2.5

3.5

CKMODE = 01

3.5

CKMODE = 10

3.5

CKMODE = 11

3.25

Sampling

time

2.5

640.5

tCONV

Total

conversion

time

(including

sampling

time)

N-bits resolution

tS +

0.5 +

IDDA_

D(ADC)

ADC

consumption

on VDDA and

VREF,

Differential

mode

fS= 5 MSPS

430

µA

fS = 1 MSPS

133

fS = 0.1 MSPS

IDDA_

(ADC)

ADC

consumption

on VDDA and

VREF,

Single-

ended mode

fS= 5 MSPS

350

fS = 1 MSPS

122

fS = 0.1 MSPS

IDD

(ADC)

ADC

consumption

on VDD per

fADC

2.4

µA/

MHz

1. Guaranteed by design.

2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).

3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.

4. Guaranteed by characterization for BGA and CSP packages. The values for LQFP packages may be different.

Table 82. 12-bit ADC characteristics(1)(2) (continued)

Sym-

bol

Parameter

Conditions

Min

Typ

Max

Unit

STM32H723VG 데이터시트(PDF) 166 Page - STMicroelectronics

STM32H723VG 데이터시트(HTML) 166 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL