STM32H723VG datasheet(190/227 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32H723xE/G

190/227

DS13313 Rev 2

USART interface characteristics

Unless otherwise specified, the parameters given in Table 106 for USART are derived from

tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 12: General operating conditions, with the following

configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Capacitive load CL = 30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

•

IO Compensation cell activated.

•

VOS level set to VOS0

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, CK, TX, RX for USART).

3. Spikes with widths above tAF(max) are not filtered.

Table 106. USART characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fCK

USART clock frequency

Master mode,

1.62 V < VDD < 3.6 V

17.0

MHz

Slave receiver mode,

1.62 V < VDD < 3.6 V

45.0

Slave transmitter mode,

1.62 V < VDD < 3.6 V

27.0

Slave transmitter mode,

2.5 V < VDD < 3.6 V

37.0

tsu(NSS)

NSS setup time

Slave mode

tker+1

th(NSS)

NSS hold time

Slave mode

tw(SCKH),

tw(SCKL)

CK high and low time

Master mode

1/fCK/2-2

1/fCK/2

1/fCK/2+2

tsu(RX)

Data input setup time

Master mode

Slave mode

1.0

th(RX)

Data input hold time

Master mode

Slave mode

2.0

tv(TX)

Data output valid time

Slave mode, ,

1.62 V < VDD < 3.6 V

12.0

Slave mode, ,

2.5 V < VDD < 3.6 V

12.0

13.5

Master mode

0.5

th(TX)

Data output hold time

Slave mode

Master mode

1. Guaranteed by characterization results.

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