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MPF7100BVBA2ES 데이터시트(PDF) 24 Page - NXP Semiconductors

부품명 MPF7100BVBA2ES
상세설명  7-channel power management integrated circuit for high performance applications
PDF  125 Pages
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제조업체  NXP [NXP Semiconductors]
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MPF7100BVBA2ES 데이터시트(HTML) 24 Page - NXP Semiconductors

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NXP Semiconductors
PF7100
7-channel power management integrated circuit for high performance applications
PF7100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 4 — 9 March 2021
24 / 125
The following figure shows startup timing with LPM_OFF = 0.
aaa-028053
treg2reset
LP_OFF State
tfirst
tpwrup_lpm
Self-Test
RESETBMCU
Regulator Outputs
Fuse load done
(internal signal)
STEST done
(internal signal)
PWRON
VSNVS1
V1P5D
UVDET
VIN
Fuse
Load
tfuseLoad
1.6 V
tvin_rise
VSNVS2
Final VSNVS2 Regulation
Final VSNVS1 Regulation
tvsnvs2_delay
Figure 8. Startup with PWRON driven high externally and bit LPM_OFF = 0
Table 17. Startup with PWRON driven high externally and LPM_OFF = 0
Symbol
Parameter
Min
Typ
Max
Unit
tvin_rise
Rise time of VIN from VPWR application to
UVDET (system dependent)
10
—
1500
µs
tfuseload
Time from VIN crossing UVDET to Fuse_Load_
done (fuse loaded correctly)
—
—
600
µs
tpwrup_lpm
Time from PWRON going high to the STEST_
done (self-test performed and passed)
—
—
700
µs
tvsnvs2_delay
Time delay from fuse load to VSNVS2 start up
—
2
—
ms
tfirst
Time from STEST_done to first slot of power up
sequence
—
—
100
µs
treg2reset
Time from first regulator enabled to
RESETBMCU asserted to guarantee 5.0 ms
PMIC boot up
[1] —
—
1.5
ms
[1]
External regulators power up sequence time (treg2reset) is programmed by OTP and may be longer than 1.5 ms.



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