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MPF7100BVBA2ES 데이터시트(PDF) 90 Page - NXP Semiconductors |
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MPF7100BVBA2ES 데이터시트(HTML) 90 Page - NXP Semiconductors |
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90 / 125 page ![]() NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 90 / 125 OTP_WD_MAX_EXPIRE causes the watchdog event to be initiated, as soon as the WD timer expires for the first time. The OTP_WDWINDOW bit selects whether the watchdog is single ended or window mode. • When OTP_WDWINDOW = 0, the WD_CLEAR flag can be cleared within 100 % of the watchdog timer. • When OTP_WDWINDOW = 1, the WD_CLEAR flag can only be cleared within the second half of the programmed watchdog timer. Clearing the WD_CLEAR flag within the first half of the watchdog window is interpreted as a failure to refresh the watchdog. aaa-028072 WD refresh OK WD_EXPIRE_CNT WD refresh NOK WD refresh NOK WD refresh NOK WD refresh NOK WD refresh NOK WD refresh NOK WD refresh NOK WD refresh OK WD refresh OK WD refresh OK WD refresh NOK WD EVENT WD refresh OK WD refresh OK WD refresh OK WD refresh OK n = WD_MAX _EXPIRE 5 4 3 2 1 0 0 WD_TIMER Expired WD refresh NOK 0 WD_TIMER Expired WD_TIMER 50 % Window WD_TIMER 100 % Window Figure 36. Watchdog timer operation The watchdog function can be enabled or disabled by writing the WD_EN bit on the I2C register map. When the I2C_SECURE_EN = 1, a secure write must be performed to change the WD_EN bit. • When WD_EN = 0, the internal watchdog timer operation is disabled. • When WD_EN = 1, the internal watchdog timer operation is enabled. The OTP_WD_EN bit is used to select the default status of the watchdog counter upon power up. The watchdog function can be programmed to be enabled or disabled during the standby state by writing the WD_STBY_EN bit on the I2C register map. When the I2C_SECURE_EN = 1, a secure write must be performed to modify the WD_STBY_EN bit. |
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