MPF7100BVBA2ES datasheet(92/125 Pages) NXP

92 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 9 March 2021

92 / 125

Bit name

Bits

LDO registers

LDOx_WDBYPASS

LDOx CONFIG1

LDOx_PG_EN

LDOx CONFIG1

LDOx_PDGRP[1:0]

LDOx CONFIG2

6:5

LDO2HW_EN

LDO2 CONFIG2

VSELECT_EN

LDO2 CONFIG2

LDOx_RUN_EN

LDOx CONFIG2

LDOx_STBY_EN

LDOx CONFIG2

LDOx_SEQ [7:0]

LDOx PWRUP

7:0

VLDOx_RUN[3:0]

LDOx RUN VOLT

3:0

VLDOx_STBY[3:0]

LDOx STBY VOLT

3:0

AMUX_EN

AMUX

A soft WD reset may require all or some regulators to be reset to their default OTP

configuration. In the event a regulator is required to keep its current configuration

during a soft WD reset, a watchdog bypass bit is provided for each regulator

(SWx_WDBYPASS / LDOx_WDBYPASS).

• When the WDBYPASS = 0, the watchdog bypass is disabled and the output of the

corresponding regulator is returned to its default OTP value during the soft WD reset.

• When the WDBYPASS = 1, the watchdog bypass is enabled and the output of the

corresponding regulator is not affected by the soft WD reset, keeping its current

configuration.

During a soft WD reset, only regulators that are activated in the power up sequence go

back to their default voltage configuration if their corresponding WDBYPASS = 0.

Switching regulators returning to their default voltage configurations gradually reach

the new output voltage using its DVS configuration. LDO regulators returning to their

default configuration changes to the default output voltage configuration instantaneously.

Regulators with WDBYPASS = 0 and which are not activated during the power up

sequence turn off immediately.

After all output voltages, have transitioned to their corresponding default values, the

device waits for at least 30 μs before returning to the run state and announces it has

finalized the soft WD reset by asserting the INTB pin, provided the WDI_I interrupt is not

masked.

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