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ADC3641 데이터시트(PDF) 47 Page - Texas Instruments |
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ADC3641 데이터시트(HTML) 47 Page - Texas Instruments |
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47 / 77 page ![]() Figure 8-45. Register 0x08 7 6 5 4 3 2 1 0 0 0 PDN CLKBUF PDN REFAMP 0 PDN A PDN B PDN GLOBAL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 8-15. Register 0x08 Field Descriptions Bit Field Type Reset Description 7-6 0 R/W 0 Must write 0 5 PDN CLKBUF R/W 0 Powers down sampling clock buffer 0: Clock buffer enabled 1: Clock buffer powered down 4 PDN REFAMP R/W 0 Powers down internal reference gain amplifier 0: REFAMP enabled 1: REFAMP powered down 3 0 R/W 0 Must write 0 2 PDN A R/W 0 Powers down ADC channel A 0: ADC channel A enabled 1: ADC channel A powered down 1 PDN B R/W 0 Powers down ADC channel B 0: ADC channel B enabled 1: ADC channel B powered down 0 PDN GLOBAL R/W 0 Global power down via SPI 0: Global power disabled 1: Global power down enabled. Power down mask (register 0x0D) determines which internal blocks are powered down. www.ti.com ADC3643 SBAS886 – OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: ADC3643 |
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