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ADC3641 데이터시트(PDF) 29 Page - Texas Instruments |
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ADC3641 데이터시트(HTML) 29 Page - Texas Instruments |
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29 / 77 page ![]() 8.3.4 Digital Down Converter The ADC364x includes an optional on-chip digital down conversion (DDC) decimation filter that can be enabled via SPI register setting. It supports complex decimation by 2, 4, 8, 16 and 32 using a digital mixer and a 32-bit numerically controlled oscillator (NCO) as shown in Figure 8-18. Furthermore it supports a mode with real decimation where the complex mixer is bypassed (NCO should be set to 0 for lowest power consumption) and the digital filter acts as a low pass filter. Internally the decimation filter calculations are performed with a 20-bit resolution in order to avoid any SNR degradation due to quantization noise. The Section 8.3.5.4 truncates to the selected resolution prior to outputting the data on the digital interface. ADC Filter I SYNC NCO 32bit Digital Interface I N N Q Q Figure 8-18. Internal Digital Decimation Filter 8.3.4.1 DDC MUX The ADC364x family contains a MUX in front of the digital decimation filter which allows the ADC channel A input to be connected to the DDC of channel B and vice versa. ADC N Digital Downconverter NCO ADC N NCO DDC MUX Figure 8-19. DDC MUX www.ti.com ADC3643 SBAS886 – OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: ADC3643 |
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