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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADC3641 데이터시트(PDF) 12 Page - Texas Instruments |
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ADC3641 데이터시트(HTML) 12 Page - Texas Instruments |
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12 / 77 page  6.10 Timing Requirements Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to T MAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS MIN NOM MAX UNIT ADC Timing Specifications tAD Aperture delay 0.85 ns tA Aperture jitter Square wave clock with fast edges 180 fs tJ Jitter on DCLKIN Serial CMOS output mode ± 50 ps Recory time from +6 dB overload condition SNR within 1 dB of expected value 1 Clock cycle tACQ Signal acquisition period, referenced to sampling clock falling edge FS = 10 Msps -TS/2 Sampling Clock Period FS = 25 Msps -TS/2 FS = 65 Msps -TS/4 tCONV Signal conversion period, referenced to sampling clock falling edge FS = 10 Msps +TS × 1/5 Sampling Clock Period FS = 25 Msps +TS × 3/8 FS = 65 Msps +TS × 5/8 Wake up time Time to valid data after coming out of power down. Internal reference. Bandgap reference enabled, single ended clock 14.6 us Bandgap reference enabled, differential clock 14.0 Bandgap reference disabled, single ended clock 1.7 ms Bandgap reference disabled, differential clock 2.1 Time to valid data after coming out of power down. External 1.6V reference. Bandgap reference enabled, single ended clock 14.6 us Bandgap reference enabled, differential clock 14.0 Bandgap reference disabled, single ended clock 1.8 ms Bandgap reference disabled, differential clock 1.7 tS,SYNC Setup time for SYNC input signal Referenced to sampling clock rising edge 500 ps tH,SYNC Hold time for SYNC input signal 600 ADC Latency Signal input to data output DDR CMOS 1 Clock cycles Serialized CMOS: 2-wire 2 Serialized CMOS: 1-wire 1 Serialized CMOS: 1/2-wire 1 Add. Latency Real decimation by 2 21 Output clock cycles Complex decimation by 2 22 Real or complex decimation by 4, 8, 16, 32 23 INTERFACE TIMING - PARALLEL DDR CMOS tPD Propagation delay: sampling clock falling edge to DCLK rising edge 3 5 7 ns tCD DCLK rising edge to output data delay Fout = 10 MSPS -0.70 -0.32 ns Fout = 25 MSPS -0.68 -0.30 Fout = 65 MSPS -0.73 -0.31 tDV Data valid, DDR CMOS Fout = 10 MSPS 49.35 49.93 ns Fout = 25 MSPS 19.66 19.77 Fout = 65 MSPS 7.42 7.51 ADC3643 SBAS886 – OCTOBER 2020 www.ti.com 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADC3643 |
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