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ADC3641 데이터시트(PDF) 55 Page - Texas Instruments

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부품명 ADC3641
상세설명  ADC364x 14-bit, 10-MSPS to 65-MSPS, Low-Noise, Low Power Dual Channel ADC
PDF  77 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

ADC3641 데이터시트(HTML) 55 Page - Texas Instruments

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Figure 8-56. Register 0x1F
7
6
5
4
3
2
1
0
LOW DR EN
DCLKIN EN
0
DCLK OB EN
2X DCLK
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-29. Register 0x1F Field Descriptions
Bit
Field
Type
Reset
Description
7
LOW DR EN
R/W
0
This bit impacts the output drive strength of the CMOS output
buffers. It can be enabled at slow speeds in order to save power
consumption but it will also degrade the rise and fall times. 0:
Low drive strength disabled.1: Low drive strength enabled.
6
DCLKIN EN
R/W
0
This bit enables the DCLKIN clock input buffer for serial CMOS
modes. Also DCLKIN EN (0x18, D4) needs to be set as well.
0: DCLKIN buffer powered down.
1: DCLKIN buffer enabled.
5
0
R/W
0
Must write 0
4
DCLK OB EN
R/W
1
This bit enables DCLK output buffer.
0: DCLK output buffer powered down.
1: DCLK output buffer enabled.
3
2X DCLK
R/W
0
This bit enables SDR output clocking with serial CMOS mode.
When this mode is enabled, DCLKIN required is twice as fast
and data is output only on rising edge of DCLK.
0: Serial data output on DCLK rising and falling edge.
1: Serial data output on DCLK rising edge only.
2-0
0
R/W
0
Must write 0
Figure 8-57. Register 0x20/21/22
7
6
5
4
3
2
1
0
FCLK PAT [7:0]
FCLK PAT [15:8]
0
0
0
0
FCLK PAT [19:16]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-30. Register 0x20/21/22 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FCLK PAT [19:0]
R/W
0xFFC00
These bits can adjust the duty cycle of the FCLK. In decimation
bypass mode the FCLK pattern gets adjusted automatically for
the different output resolutions. Table 8-31 shows the proper
FCLK pattern values for 1-wire and 1/2-wire in real/complex
decimation.
Table 8-31. FCLK Pattern for different resolution based on interface
DECIMATION
OUTPUT RESOLUTION
2-WIRE
1-WIRE
1/2-WIRE
REAL DECIMATION
14-bit
Use Default
0xFE000
Use Default
16-bit
0xFF000
18-bit
0xFF800
20-bit
0xFFC00
COMPLEX
DECIMATION
14-bit
0xFFFFF
0xFFFFF
16-bit
18-bit
20-bit
www.ti.com
ADC3643
SBAS886 – OCTOBER 2020
Copyright © 2020 Texas Instruments Incorporated
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