Z8F082ASH020SC datasheet(64/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Interrupt Controller

Z8 Encore! XP® F08xA Series

Product Specification

Interrupt Controller

Overview

The interrupt controller on the XP 8K Series products prioritizes the interrupt requests

from the on-chip peripherals and the GPIO port pins. The features of the interrupt control-

ler include the following:

• 20 unique interrupt vectors:

–

14 GPIO port pin interrupt sources (two are shared)

–

10 on-chip peripheral interrupt sources (two are shared)

• Flexible GPIO interrupts

–

8 selectable rising and falling edge GPIO interrupts

–

4 dual-edge interrupts

• 3 levels of individually programmable interrupt priority

• Watch-Dog Timer and Low Voltage Detect (LVD) can be configured to generate an inter-

rupt

Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly

manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt

service routine is involved with the exchange of data, status information, or control infor-

mation between the CPU and the interrupting peripheral. When the service routine is com-

pleted, the CPU returns to the operation from which it was interrupted.

The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,

the interrupt controller has no effect on operation. Refer to the eZ8 CPU User Manual for

more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Man-

ual is available for download at www.zilog.com.

Interrupt Vector Listing

Table 31 lists all of the interrupts available in order of priority. The interrupt vector is

stored with the most significant byte (MSB) at the even Program Memory address and the

least significant byte (LSB) at the following odd Program Memory address.

Some port interrupts are not available on the 8- and 20-pin packages. The ADC interrupt is

unavailable on devices not containing an ADC.

Note:

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