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Z8F082ASH020SC 데이터시트(PDF) 57 Page - Zilog, Inc.

부품명 Z8F082ASH020SC
상세설명  Z8 Encore XP-R F08xA Series with eXtended Peripherals
PDF  244 Pages
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제조업체  ZILOG [Zilog, Inc.]
홈페이지  http://www.zilog.com
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Z8F082ASH020SC 데이터시트(HTML) 57 Page - Zilog, Inc.

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PS024705-0405
P R E L I M I N A R Y
General-Purpose I/O
Z8 Encore! XP® F08xA Series
Product Specification
39
DD[7:0]—Data Direction
These bits control the direction of the associated port pin. Port Alternate Function opera-
tion overrides the Data Direction register setting.
0 = Output. Data in the Port A–D Output Data register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–D Input Data Reg-
ister. The output driver is tristated.
Port A–D Alternate Function Sub-Registers
The Port A–D Alternate Function sub-register (Table 19) is accessed through the Port A–
D Control register by writing 02H to the Port A–D Address register. The Port A–D Alter-
nate Function sub-registers enable the alternate function selection on pins. If disabled, pins
functions as GPIO. If enabled, select one of four alternate functions using alternate func-
tion set subregisters 1 and 2 as described in the “Port A–D Alternate Function Set 1 Sub-
Registers” on page 42
and “Port A–D Alternate Function Set 2 Sub-Registers” on page 42.
Refer
to the “GPIO Alternate Functions” on page 32 to determine the alternate function asso-
ciated with each port pin.
Do not enable alternate functions for GPIO port pins for which there is no
associated alternate function. Failure to follow this guideline can result in
unpredictable operation.
AF[7:0]—Port Alternate Function enabled
0 = The port pin is in normal mode and the DDx bit in the Port A–D Data Direction sub-
register determines the direction of the pin.
Table 18. Port A–D Data Direction Sub-Registers (PxDD)
BITS
7
6
5
4
3
2
1
0
FIELD
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
RESET
1
111
11
11
R/W
R/WR/W
R/WR/W
R/WR/W
R/WR/W
ADDR
If 01H in Port A–D Address Register, accessible through the Port A–D Control Register
Table 19. Port A–D Alternate Function Sub-Registers (PxAF)
BITS
7
6
5
4
3
2
1
0
FIELD
AF7
AF6
AF5
AF4
AF3
AF2
AF1
AF0
RESET
00H (Ports A–C); 01H (Port D)
R/W
R/W
ADDR
If 02H in Port A–D Address Register, accessible through the Port A–D Control Register
Caution:



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