전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Z8F082ASH020SC 데이터시트(PDF) 29 Page - Zilog, Inc.

부품명 Z8F082ASH020SC
상세설명  Z8 Encore XP-R F08xA Series with eXtended Peripherals
PDF  244 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  ZILOG [Zilog, Inc.]
홈페이지  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8F082ASH020SC 데이터시트(HTML) 29 Page - Zilog, Inc.

Back Button Z8F082ASH020SC Datasheet HTML 25Page - Zilog, Inc. Z8F082ASH020SC Datasheet HTML 26Page - Zilog, Inc. Z8F082ASH020SC Datasheet HTML 27Page - Zilog, Inc. Z8F082ASH020SC Datasheet HTML 28Page - Zilog, Inc. Z8F082ASH020SC Datasheet HTML 29Page - Zilog, Inc. Z8F082ASH020SC Datasheet HTML 30Page - Zilog, Inc. Z8F082ASH020SC Datasheet HTML 31Page - Zilog, Inc. Z8F082ASH020SC Datasheet HTML 32Page - Zilog, Inc. Z8F082ASH020SC Datasheet HTML 33Page - Zilog, Inc. Next Button
Zoom Inzoom in Zoom Outzoom out
 29 / 244 page
background image
PS024705-0405
P R E L I M I N A R Y
Pin Description
Z8 Encore! XP® F08xA Series
Product Specification
11
Pin Characteristics
Table 4 provides detailed information about the characteristics for each pin available on
the Z8 Encore! XP® F08xA Series 20- and 28-pin devices. Data in Table 4 is sorted alpha-
betically by the pin symbol mnemonic.
PB6 and PB7 are available only in those devices without ADC.
VSS
I
Digital Ground.
AVSS
I
Analog Ground.
Note: The AVDD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by
PB6 and PB7 on 28-pin packages without ADC.
Table 4. Pin Characteristics (20- and 28-pin Devices)
Symbol
Mnemonic Direction
Reset
Direction
Active Low
or
Active High
Tristate
Output
Internal Pull-
up
or Pull-down
Schmitt
Trigger
Input
Open Drain
Output
5V
Tolerance
AVDD
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
AVSS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
NA
DBG
I/O
I
N/A
Yes
No
Yes
Yes
Yes
PA[7:0]
I/O
I
N/A
Yes
Programmable
Pull-up
Yes
Yes,
Programmable
PA[7:2]
only
PB[7:0]
I/O
I
N/A
Yes
Programmable
Pull-up
Yes
Yes,
Programmable
PB[7:6]
only
PC[7:0]
I/O
I
N/A
Yes
Programmable
Pull-up
Yes
Yes,
Programmable
PC[7:3]
only
RESET/
PD0
I/O
I/O
(defaults to
RESET)
Low (in
Reset mode)
Yes (PD0
only)
programmable
for PD0;
always on for
RESET
Yes
programmable
for PD0; always
on for RESET
Yes
VDD
N/A
N/A
N/A
N/A
N/A
N/A
VSS
N/A
N/A
N/A
N/A
N/A
N/A
Table 3. Signal Descriptions (Continued)
Signal Mnemonic
I/O
Description
Note:



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com