Z8F082ASH020SC datasheet(75/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Interrupt Controller

Z8 Encore! XP® F08xA Series

Product Specification

Because these shared interrupts are edge-triggered, it is possible to generate an interrupt

just by switching from one shared source to another. For this reason, an interrupt must be

disabled before switching between sources.

PA6CS—PA6/Comparator Selection

0 = PA6 is used for the interrupt for PA6CS interrupt request.

1 = The Comparator is used for the interrupt for PA6CS interrupt request.

Reserved—Must be 0.

Interrupt Control Register

The Interrupt Control (IRQCTL) register (Table 46) contains the master enable bit for all

interrupts.

IRQE—Interrupt Request Enable

This bit is set to 1 by executing an EI (Enable Interrupts) or IRET (Interrupt Return)

instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI

instruction, eZ8 CPU acknowledgement of an interrupt request, Reset or by a direct regis-

ter write of a 0 to this bit.

0 = Interrupts are disabled.

1 = Interrupts are enabled.

Reserved—Must be 0.

Table 45. Shared Interrupt Select Register (IRQSS)

BITS

FIELD

Reserved

PA6CS

Reserved

RESET

000

R/W

R/WR/W

ADDR

FCEH

Table 46. Interrupt Control Register (IRQCTL)

BITS

FIELD

IRQE

Reserved

RESET

000

R/W

RRR

ADDR

FCFH

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