Z8F082ASH020SC datasheet(116/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

UART

Z8 Encore! XP® F08xA Seriess

Product Specification

Reserved—Must be 0.

NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive

Data register resets this bit to 0.

0 = The current byte is not the first data byte of a new frame.

1 = The current byte is the first data byte of a new frame.

MPRX—Multiprocessor Receive

Returns the value of the most recent multiprocessor bit received. Reading from the UART

Receive Data register resets this bit to 0.

UART Control 0 and Control 1 Registers

The UART Control 0 and Control 1 registers (Tables 64 and 65) configure the properties

of the UART’s transmit and receive operations. The UART Control registers must not be

written while the UART is enabled.

TEN—Transmit Enable

This bit enables or disables the transmitter. The enable is also controlled by the CTS signal

and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is

enabled.

0 = Transmitter disabled.

1 = Transmitter enabled.

REN—Receive Enable

This bit enables or disables the receiver.

0 = Receiver disabled.

1 = Receiver enabled.

CTSE—CTS Enable

0 = The CTS signal has no effect on the transmitter.

1 = The UART recognizes the CTS signal as an enable control from the transmitter.

R/W

ADDR

F44H

Table 64. UART Control 0 Register (U0CTL0)

BITS

FIELD

TEN

REN

CTSE

PEN

PSEL

SBRK

STOP

LBEN

RESET

000

R/W

R/WR/W

ADDR

F42H

Table 63. UART Status 1 Register (U0STAT1)

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