Z8F082ASH020SC datasheet(137/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Analog-to-Digital Converter

Z8 Encore! XP® F08xA Series

Product Specification

119

ADC Control/Status Register 1

The second ADC Control register configures the input buffer stage, enables the threshold

interrupts and contains the status of both threshold triggers.

REFSELH—Voltage Reference Level Select High Bit; in conjunction with the Low bit

(REFSELL) in ADC Control Register 0, this determines the level of the internal voltage ref-

erence; the following details the effects of {REFSELH, REFSELL}; this reference is inde-

pendent of the Comparator reference

00= Internal Reference Disabled, reference comes from external pin

01= Internal Reference set to 1.0 V

10= Internal Reference set to 2.0 V (default)

11= Reserved

ALMHST—Alarm High Status; this bit can only be set by hardware and must be written

with a 1 to clear

0= No alarm occurred.

1= A high threshold alarm occurred.

ALMLST—Alarm Low Status; this bit can only be set by hardware and must be written

with a 1 to clear

0= No alarm occurred.

1= A low threshold alarm occurred.

ALMHEN—Alarm High Enable

0= Alarm interrupt for high threshold is disabled. The alarm status bit remains set when

the alarm threshold is passed.

1= High threshold alarm interrupt is enabled.

ALMLEN—Alarm Low Enable

0= Alarm interrupt for low threshold is disabled. The alarm status bit remains set when the

alarm threshold is passed.

1= Low threshold alarm interrupt is enabled.

BUFMODE[2:0] - Input Buffer Mode Select

000 = Single-ended, unbuffered input

001 = Single-ended, buffered input with unity gain

010 = Reserved

011 = Reserved

Table 71. ADC Control/Status Register 1 (ADCCTL1)

BITS

FIELD

REFSELH

ALMHST

ALMLST

ALMHEN

ALMLEN

BUFMODE[2:0]

RESET

000

R/W

R/WR/W

ADDR

F71H

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