Z8F082ASH020SC datasheet(189/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

eZ8 CPU Instruction Set

Z8 Encore! XP® F08xA Series

Product Specification

171

Assembly Language Syntax

For proper instruction execution, eZ8 CPU assembly language syntax requires that the

operands be written as ‘destination, source’. After assembly, the object code usually has

the operands in the order ’source, destination’, but ordering is opcode-dependent. The fol-

lowing instruction examples illustrate the format of some basic assembly instructions and

the resulting object code produced by the assembler. This binary format must be followed

by users that prefer manual program coding or intend to implement their own assembler.

Example 1: If the contents of Registers 43H and 08H are added and the result is stored in

43H, the assembly syntax and resulting object code is:

Example 2: In general, when an instruction format requires an 8-bit register address, that

address can specify any register location in the range 0–255 or, using Escaped Mode

Addressing, a Working Register R0–R15. If the contents of Register 43H and Working

object code is:

See the device-specific Product Specification to determine the exact register file range

available. The register file size varies, depending on the device type.

eZ8 CPU Instruction Notation

In the eZ8 CPU Instruction Summary and Description sections, the operands, condition

codes, status flags, and address modes are represented by a notational shorthand that is

described in Table 106

Table 104. Assembly Language Syntax Example 1

Assembly Language Code

ADD

43H,

08H

(ADD dst, src)

Object Code

(OPC src, dst)

Table 105. Assembly Language Syntax Example 2

Assembly Language Code

ADD

43H,

(ADD dst, src)

Object Code

(OPC src, dst)

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