전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

DS31256+ 데이터시트(PDF) 60 Page - Maxim Integrated Products

부품명 DS31256+
상세설명  256-Channel, High-Throughput HDLC Controller
PDF  183 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  MAXIM [Maxim Integrated Products]
홈페이지  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS31256+ 데이터시트(HTML) 60 Page - Maxim Integrated Products

Back Button DS31256+ Datasheet HTML 56Page - Maxim Integrated Products DS31256+ Datasheet HTML 57Page - Maxim Integrated Products DS31256+ Datasheet HTML 58Page - Maxim Integrated Products DS31256+ Datasheet HTML 59Page - Maxim Integrated Products DS31256+ Datasheet HTML 60Page - Maxim Integrated Products DS31256+ Datasheet HTML 61Page - Maxim Integrated Products DS31256+ Datasheet HTML 62Page - Maxim Integrated Products DS31256+ Datasheet HTML 63Page - Maxim Integrated Products DS31256+ Datasheet HTML 64Page - Maxim Integrated Products Next Button
Zoom Inzoom in Zoom Outzoom out
 60 / 183 page
background image
DS31256 256-Channel, High-Throughput HDLC Controller
60 of 183
6.5 BERT
The BERT block is capable of generating and detecting the following patterns:
The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS
A repetitive pattern from 1 to 32 bits in length
Alternating (16-bit) words that flip every 1 to 256 words
The BERT receiver has a 32-bit bit counter and a 24-bit error counter. It can generate interrupts upon
detecting a bit error, a change in synchronization, or if an overflow occurs in the bit and error counters.
See Section 5 for details on status bits and interrupts from the BERT block. To activate the BERT block,
the host must configure the BERT mux (Figure 6-7). In channelized applications, the host must also
configure the Layer 1 state machine to send/obtain data to/from the BERT block through the Layer 1
configuration registers (Section 6.3).
Figure 6-7. BERT Mux Diagram
Port 0 (slow)
Port 1 (slow)
Port 2 (slow)
Port 3 (slow)
Port 4 (slow)
Port 5 (slow)
BERT
Mux
BERT
BLOCK
SBERT STATUS
BIT IN SM
INTERNAL CONTROL AND
CONFIGURATION BUS
Port 13 (slow)
Port 14 (slow)
Port 15 (slow)
Port 0 (fast)
Port 1 (fast)
BERT SELECT (5)
IN THE MASTER CONFIGURATION REGISTER
Port 2 (fast)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com