DS31256+ datasheet(18/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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3.2 Serial Port Interface Signal Description

Signal Name:

RC0 to RC15

Signal Description:

Receive Serial Clock

Signal Type:

Input

Data can be clocked into the device either on rising edges (normal clock mode) or falling edges (inverted clock

mode) of RC. This is programmable on a per port basis. RC0–RC2 can operate at speeds up to 52MHz.

RC3–RC15 can operate at speeds up to 10MHz. Unused signals should be wired low.

Signal Name:

RD0 to RD15

Signal Description:

Receive Serial Data

Signal Type:

Input

Can be sampled either on the rising edge of RC (normal clock mode) or the falling edge of RC (inverted clock

mode). Unused signals should be wired low.

Signal Name:

RS0 to RS15

Signal Description:

Receive Serial Data Synchronization Pulse

Signal Type:

Input

This is a one-RC clock-wide synchronization pulse that can be applied to the DS31256 to force byte/frame

alignment. The applied sync-signal pulse can be either active high (normal sync mode) or active low (inverted

sync mode). The RS signal can be sampled either on the falling edge or on rising edge of RC (Table 3-B). The

applied sync pulse can be during the first RC clock period of a 193/256/512/1024-bit frame or it can be applied

1/2, 1, or 2 RC clocks early. This input sync signal resets a counter that rolls over at a count of either 193 (T1

mode) or 256 (E1 mode) or 512 (4.096MHz mode) or 1024 (8.192MHz mode) RC clocks. It is acceptable to pulse

the RS signal once to establish byte boundaries and allow the DS31256 to track the byte/frame boundaries by

counting RC clocks. If the incoming data does not require alignment to byte/frame boundaries, this signal should

be wired low.

Table 3-B. RS Sampled Edge

SIGNAL

NORMAL RC CLOCK MODE

INVERTED RC CLOCK MODE

0 RC Clock Early Mode

Falling Edge

Rising Edge

1/2 RC Clock Early Mode

Rising Edge

Falling Edge

1 RC Clock Early Mode

Falling Edge

Rising Edge

2 RC Clock Early Mode

Falling Edge

Rising Edge

Signal Name:

TC0 to TC15

Signal Description:

Transmit Serial Clock

Signal Type:

Input

Data can be clocked out of the device either on rising edges (normal clock mode) or falling edges (inverted clock

mode) of TC. This is programmable on a per port basis. TC0 and TC1 can operate at speeds up to 52MHz. TC2–

TC15 can operate at speeds up to 10MHz. Unused signals should be wired low.

Signal Name:

TD0 to TD15

Signal Description:

Transmit Serial Data

Signal Type:

Output

This can be updated either on the rising edge of TC (normal clock mode) or the falling edge of TC (inverted clock

mode). Data can be forced high.

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