DS31256+ datasheet(3/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

3 of 183

9.2.5

DMA Channel Configuration RAM .................................................................................................... 102

9.3

TRANSMIT SIDE .......................................................................................................................105

9.3.1

Overview ........................................................................................................................................... 105

9.3.2

Packet Descriptors ............................................................................................................................ 114

9.3.3

Pending Queue ................................................................................................................................. 116

9.3.4

Done Queue...................................................................................................................................... 120

9.3.5

DMA Configuration RAM................................................................................................................... 125

10.

PCI BUS.......................................................................................................................130

10.1

GENERAL DESCRIPTION OF OPERATION ...................................................................................130

10.1.1

PCI Read Cycle................................................................................................................................. 131

10.1.2

PCI Write Cycle................................................................................................................................. 132

10.1.3

PCI Bus Arbitration............................................................................................................................ 133

10.1.4

PCI Initiator Abort.............................................................................................................................. 133

10.1.5

PCI Target Retry ............................................................................................................................... 134

10.1.6

PCI Target Disconnect...................................................................................................................... 134

10.1.7

PCI Target Abort ............................................................................................................................... 135

10.1.8

PCI Fast Back-to-Back...................................................................................................................... 136

10.2

PCI CONFIGURATION REGISTER DESCRIPTION .........................................................................137

10.2.1

Command Bits (PCMD0)................................................................................................................... 138

10.2.2

Status Bits (PCMD0) ......................................................................................................................... 139

10.2.3

Command Bits (PCMD1)................................................................................................................... 143

10.2.4

Status Bits (PCMD1) ......................................................................................................................... 144

11.

LOCAL BUS ................................................................................................................147

11.1

GENERAL DESCRIPTION ...........................................................................................................147

11.1.1

PCI Bridge Mode............................................................................................................................... 149

11.1.2

Configuration Mode........................................................................................................................... 151

11.2

LOCAL BUS BRIDGE MODE CONTROL REGISTER DESCRIPTION..................................................153

11.3

EXAMPLES OF BUS TIMING FOR LOCAL BUS PCI BRIDGE MODE OPERATION .............................155

12.

JTAG............................................................................................................................163

12.1

JTAG DESCRIPTION ................................................................................................................163

12.2

TAP CONTROLLER STATE MACHINE DESCRIPTION ...................................................................164

12.3

INSTRUCTION REGISTER AND INSTRUCTIONS ............................................................................166

12.4

TEST REGISTERS.....................................................................................................................167

13.

AC CHARACTERISTICS.............................................................................................168

14.

REVISION HISTORY ...................................................................................................176

15.

PACKAGE INFORMATION .........................................................................................177

15.1

256-PIN PBGA (27MM X 27MM) ...............................................................................................177

16.

THERMAL CHARACTERISTICS.................................................................................178

17.

APPLICATIONS...........................................................................................................179

17.1

16 PORT T1 OR E1 WITH 256 HDLC CHANNEL SUPPORT.........................................................180

17.2

DUAL T3 WITH 256 HDLC CHANNEL SUPPORT ........................................................................181

17.3

SINGLE T3 WITH 512 HDLC CHANNEL SUPPORT......................................................................182

17.4

SINGLE T3 WITH 672 HDLC CHANNEL SUPPORT......................................................................183

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