DS31256+ datasheet(91/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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Figure 9-4. Receive Packet Descriptors

dword 0

Data Buffer Address (32)

dword 1

BUFS (3)

Byte Count (13)

Next Descriptor Pointer (16)

dword 2

Timestamp (24)

HDLC Channel (8)

dword 3

unused (32)

Note: The organization of the receive descriptor is not affected by the enabling of Big Endian.

dword 0; Bits 0 to 31/Data Buffer Address. Direct 32-bit starting address of the data buffer that is associated

with this receive descriptor.

dword 1; Bits 0 to 15/Next Descriptor Pointer. This 16-bit value is the offset from the receive descriptor base

address of the next descriptor in the chain. Only valid if buffer status = 001 or 010. Note: This is an index, not

absolute address.

dword 1; Bits 16 to 28/Byte Count. Number of bytes stored in the data buffer. Maximum is 8188 Bytes (0000h =

0 Bytes / 1FFCh = 8188 Bytes).

dword 1; Bits 29 to 31/Buffer Status. Must be one of the three states listed below.

001 = first buffer of a multiple buffer packet

010 = middle buffer of a multiple buffer packet

100 = last buffer of a multiple or single buffer packet (equivalent to EOF)

dword 2; Bits 0 to 7/HDLC Channel Number. HDLC channel number, which can be from 1 to 256.

00000000 (00h) = HDLC channel number 1

11111111 (FFh) = HDLC channel number 256

dword 2; Bits 8 to 31/Timestamp. When each descriptor is written into memory by the DMA, this 24-bit

timestamp is provided to keep track of packet arrival times. The timestamp is based on the PCLK frequency

divided by 16. For a 33MHz PCLK, the timestamp increments every 485ns and rolls over every 8.13 seconds. For

a 25MHz clock, the timestamp increments every 640ns and rolls over every 10.7 seconds. The host can calculate

the difference in packets’ arrival times by knowing the PCLK frequency and then taking the difference in

timestamp readings between consecutive packet descriptors.

dword 3; Bits 0 to 31/Unused. Not written to by the DMA. Can be used by the host. Application Note: dword 3

is used by the transmit DMA and, in store and forward applications, the receive and transmit packet descriptors

have been designed to eliminate the need for the host to groom the descriptors before transmission. In these type of

applications, the host should not use dword 3 of the receive packet descriptor.

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