DS31256+ datasheet(42/183 Pages) MAXIM

42 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

42 of 183

ISDMA

Interrupt Mask Register for SDMA

002Ch

Bit #

Name

RLBRE

RLBR

ROVFL

RLENC

RABRT

RCRCE

n/a

Default

Bit #

Name

TDQWE

TDQW

TPQR

TUDFL

RDQWE

RDQW

RSBRE

RSBR

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 2/Status Bit for Receive HDLC CRC Error (RCRCE)

0 = interrupt masked

1 = interrupt unmasked

Bit 3/Status Bit for Receive HDLC Abort Detected (RABRT)

0 = interrupt masked

1 = interrupt unmasked

Bit 4/Status Bit for Receive HDLC Length Check (RLENC)

0 = interrupt masked

1 = interrupt unmasked

Bit 5/Status Bit for Receive FIFO Overflow (ROVFL)

0 = interrupt masked

1 = interrupt unmasked

Bit 6/Status Bit for Receive DMA Large Buffer Read (RLBR)

0 = interrupt masked

1 = interrupt unmasked

Bit 7/Status Bit for Receive DMA Large Buffer Read Error (RLBRE)

0 = interrupt masked

1 = interrupt unmasked

Bit 8/Status Bit for Receive DMA Small Buffer Read (RSBR)

0 = interrupt masked

1 = interrupt unmasked

Bit 9/Status Bit for Receive DMA Small Buffer Read Error (RSBRE)

0 = interrupt masked

1 = interrupt unmasked

Bit 10/Status Bit for Receive DMA Done-Queue Write (RDQW)

0 = interrupt masked

1 = interrupt unmasked

Bit 11/Status Bit for Receive DMA Done-Queue Write Error (RDQWE)

0 = interrupt masked

1 = interrupt unmasked

Bit 12/Status Bit for Transmit FIFO Underflow (TUDFL)

0 = interrupt masked

1 = interrupt unmasked

DS31256+ 데이터시트(PDF) 42 Page - Maxim Integrated Products

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