VSC8658 datasheet(13/95 Pages) MICROSEMI

13 / 95 page

Product Overview

VMDS-10242 VSC8658 Datasheet Revision 4.1

3.2

Block Diagram

The following illustration shows the primary functional blocks of the VSC8658 device.

Dual, high-performance, 1.25 Gbps SerDes

Maximizes receive jitter tolerance and minimizes transmit

jitter (in comparison to single SerDes architectures)

Compliance with IEEE standard 802.3 (10BASE-T,

100BASE-TX, 1000BASE-T, 1000BASE-X, 100BASE-FX)

Ensures seamless deployment in devices throughout

existing copper networks while maintaining excellent

tolerance to ambient electronic noise and any

substandard cabling

Support for frame sizes greater than 16 kilobytes at all

device throughput settings and programmable

synchronization FIFO buffers

Provides for maximum Jumbo frame sizes on custom

SANs and LANs

Four integrated and programmable LED direct drivers per

port, on-chip filtering and support for bi-color LEDs

Eliminates the need for external components, lowers EMI

generation, and lowers design cost

Multiple built-in testing facilities, including near-end, far-

end, and connector loopback; Ethernet packet generator

with CRC error counter

Lowers system or device development, lowers

deployment costs, and decreases time-to-market

Serial LED interface option

Enables design flexibility

Support for the CISCO specification for serial gigabit

media-independent interface version 1.7 (SGMII (v1.7),

for 1000BASE-X MACs, for IEEE standard 1149.1-1999

JTAG boundary scan, and for IEEE standard 1149.6

AC-JTAG scan.

Saves manufacturing and quality assurance costs

VeriPHY™ cable diagnostics

Enables system managers to simplify deployment and

improve Gigabit Ethernet network performance

Table 1 •

Features and Benefits (continued)

Feature

Benefit

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