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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32F730V8 데이터시트(PDF) 30 Page - STMicroelectronics |
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STM32F730V8 데이터시트(HTML) 30 Page - STMicroelectronics |
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30 / 202 page  Functional overview STM32F730x8 30/202 DS12536 Rev 2 Figure 8. Power supply supervisor interconnection with internal reset OFF The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 9). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry must be disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD. All packages, except for the LQFP100, allow to disable the internal reset through the PDR_ON signal when connected to VSS. Figure 9. PDR_ON control with internal reset OFF MS31383V4 NRST VDD PDR_ON External VDD power supply supervisor Ext. reset controller active when VDD < 1.7 V VDD Application reset signal VSS MS19009V7 V DD time PDR = 1.7 V time NRST PDR_ON PDR_ON Reset by other source than power supply supervisor |
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