STM32WLE4JC datasheet(27/146 Pages) STMICROELECTRONICS

27 / 146 page

DS13105 Rev 9

27/146

STM32WLE5/E4xx

Functional overview

Five BOR thresholds can be selected through option bytes.

During power-on, BOR keeps the device under reset until the supply voltage VDD reaches

the specified VBORx threshold:

•

When VDD drops below the selected threshold, a device reset is generated.

•

When VDD is above the VBORx upper limit, the device reset is released and the system

can start.

The devices feature an embedded PVD (programmable voltage detector) that monitors the

VDD power supply and compares it with the VPVD threshold. An interrupt can be generated

when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD

threshold. The interrupt service routine can then generate a warning message and/or put

the MCU into a safe state.

The PVD is enabled by software and can be configured to monitor the VDD supply level

needed for the sub-GHz radio operation. For this, the PVD must select its lowest threshold,

and the PVD and the wakeup must be enabled by the EWPVD bit in PWR_CR3 register.

Only a voltage drop below the PVD level generates a wakeup event.

In addition, the devices embed a PVM (peripheral voltage monitor) that compares the

independent supply voltage VDDA with a fixed threshold to ensure that the peripheral is in its

functional supply range.

Finally, a radio end-of-life monitor provides information on the VDD supply when VDD is too

low to operate the sub-GHz radio. When reaching the EOL level, the software must stop all

radio activity in a safe way.

3.9.3

Linear voltage regulator

Two embedded linear voltage regulators supply all the digital circuitries, except for the

Standby circuitry and the Backup domain. The main regulator (MR) output voltage (VCORE)

can be programmed by software to two different power ranges (range 1 and range 2), to

optimize the consumption depending on the system maximum operating frequency.

The voltage regulators are always enabled after a reset. Depending on the application

modes, the VCORE supply is provided either by the main regulator or by the low-power

regulator (LPR).

When MR is used, a dynamic voltage scaling is proposed to optimize power as follows:

•

range 1: high-performance range

The system clock frequency can be up to 48 MHz. The Flash memory access time for

read access is minimum. Write and erase operations are possible.

•

range 2: low-power range

The system clock frequency can be up to 16 MHz.The Flash memory access time for a

read access is increased as compared to range 1. Write and erase operations are

possible.

Note:

MR is supplied by VDD during power-on or at wakeup from Stop1, Stop2, Standby or

Shutdown mode. MR is powered by LDO/SMPS after these transition phases.

3.9.4

VBAT operation

The VBAT pin is used to power the device VBAT domain (RTC, LSE and backup registers)

from an external battery, an external super-capacitor, or from VDD when no external battery

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