SPC572L60F2 datasheet(64/112 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC572Lx

64/112

DocID027866 Rev 5

The following supplies are involved:

•

HV—High voltage external power supply for voltage regulator module. It is shorted with

VDD_HV_IO.

•

BV—High voltage external power supply for internal ballast module. It is shorted with

VDD_HV_IO.

•

LV—Low voltage internal power supply for core, PLL and flash digital logic. This is

generated by the internal voltage regulator but provided outside to connect stability

capacitor. It is split into three further domains to ensure noise isolation between critical

LV modules within the device:

–

LV_COR—Low voltage supply for the core. It is also used to provide supply for

PLL through double bonding.

–

LV_FLA—Low voltage supply for code flash module. It is supplied with dedicated

ballast and shorted to LV_COR through double bonding.

–

LV_PLL—Low voltage supply for PLL. It is shorted to LV_COR through double

bonding.

Table 31. Voltage regulator electrical characteristics

Symbol

Parameter

Conditions(1)

Value(2)

Unit

Min

Typ

Max

CREG

SR Internal voltage regulator stability

external capacitance

—1.1

2.2(3)

2.97

µF

RREG

SR Stability capacitor equivalent serial

resistance

Total resistance including

board track

1—

CDECREGn SR Internalvoltage regulator decoupling

external capacitance

—

100

135

RDECREGn SR Stability capacitor equivalent serial

resistance

—1

—

CDECBV

SR Decoupling capacitance(4) ballast

VDD_HV_IO_MAIN/VSS pair

—

4(3)

—µF

CDECHV

SR Decoupling capacitance regulator

supply

VDD_HV_IO_MAIN/VSS pair

100

—

CDECFLA

SR Decoupling capacitance for flash

supply

VDD_HV_FLA/VSS pair

100

—

VMREG

CC Main regulator output voltage

Before trimming

1.19

1.26

1.33(5)

After trimming

1.16

1.28

1.32(6)

IDDMREG SR Main regulator current provided to

VDD_LV domain

—

125

ΔIDDMREG SR Main regulator current variation

20 µs observation window

–60

—

IMREGINT(7) D Main regulator current consumption

—

1.5

3.0

1. VDD = 5.0 V ± 10%, TA = –40 / 125 °C, unless otherwise specified.

2. All values need to be confirmed during device validation.

3. Recommended X7R or X5R ceramic –50% / +35% variation across process, temperature, voltage and after aging.

4. This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical

value is in the range of 470 nF.

5. At power-up condition before trimming at 27 °C, no load.

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