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SPC572L60F2 데이터시트(PDF) 41 Page - STMicroelectronics

부품명 SPC572L60F2
상세설명  32-bit Power Architecture® based MCU for automotive powertrain applications
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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SPC572Lx
Electrical characteristics
111
1. PLL0IN clock retrieved directly from either Internal RC Oscillator (IRCOSC) or External Oscillator (XOSC) clock. Input
characteristics are granted when using XOSC.
2. fPLL0IN frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure PFD input signal is in the range of
8MHz-20MHz.
3.
VDD_LV noise due to application in the range VDD_LV = 1.25 V ± 5% with frequency below PLL bandwidth (40 kHz) is
filtered.
Table 21. External oscillator electrical specifications
Symbol
C
Parameter
Conditions
Value
Unit
Min
Max
fXTAL
CC D Crystal frequency range(1)
—
—
—
48
MHz
> 8
20
> 20
40
tcst
CC T Crystal start-up time(2)(3)
——
5
ms
trec
CC T Crystal recovery time(4)
——
0.5
ms
VIHEXT CC D EXTAL input high voltage
(External Reference)
VREF = 0.28 * VDD_HV_IO_JTAG
VREF + 0.6
—
V
VILEXT CC D EXTAL input low voltage(5)
VREF = 0.28 * VDD_HV_IO_JTAG
—VREF - 0.6
V
CS_EXTAL CC T Total on-chip stray
capacitance on EXTAL pin
—
—
2.5 + value
from
Table 22
pF
CS_XTAL CC T Total on-chip stray
capacitance on XTAL pin
—
—
2.5 + value
from
Table 22
pF
gm
CC D Oscillator Transconductance
TJ =-40 °C to
150 °C
4.5 V <
VDD_HV_IO <
5.5 V
fXTAL ≤ 8MHz
2.6
11.0
mA/V
DfXTAL ≤ 20 MHz
7.9
26.0
DfXTAL ≤ 40 MHz
10.4
34.0
IXTAL
CC D XTAL current(6)
TJ = 150 °C
—
14
mA
VHYS
CC D Comparator Hysteresis
TJ = 150 °C
0.1
1.0
V
1. The range is selectable by DCF record.
2. This value is determined by the crystal manufacturer and board design.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load
capacitor value.
5. Applies to an external clock input and not to crystal mode.
6. IXTAL is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. Test circuit is shown in
Figure 11.



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