SPC572L60F2 datasheet(83/112 Pages) STMICROELECTRONICS

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SPC572Lx

Electrical characteristics

111

Figure 31. DSPI PCS strobe (PCSS) timing (master mode)

3.17.2.1.3 DSPI Master Mode – Output Only

PCSx

PCSS

tPCSC

tPASC

Table 43. DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,

CPOL = 0 or 1, continuous SCK clock(1)(2)

Symbol

Characteristic

Condition

Value

Unit

Pad drive

Load

Min

Max

1tSCK

SCK cycle time

LVDS

15 pF

to 50 pF

differential

25.0

—

2tCSV

PCS valid after

SCK(3)

(SCK with 50 pF

differential load cap.)

Very strong

25 pF

—

6.0

Strong

50 pF

—

10.5

3tCSH

PCS hold after

SCK(3)

(SCK with 50 pF

differential load cap.)

Very strong

0 pF

–4.0

—

Strong

0pF

–4.0

—ns

4tSDC

SCK duty cycle

(SCK with 50 pF

differential load cap.)

LVDS

15 pF

to 50 pF

differential

1/2tSCK –2 1/2tSCK +2 ns

SOUT data valid time (after SCK edge)

5tSUO

SOUT data valid time

from SCK(4)

SOUT and SCK drive strength

LVDS

15 pF

to 50 pF

differential

—8.0

SOUT data hold time (after SCK edge)

6tHO

SOUT data hold time

after SCK(4)

SOUT and SCK drive strength

LVDS

15 pF

to 50 pF

differential

0.0

—

1. All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS with pad

driver strength as defined. Timing may degrade for weaker output drivers.

2. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

3. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This

timing value is due to pad delays and signal propagation delays.

4. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

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