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STM32WB50CG 데이터시트(PDF) 98 Page - STMicroelectronics

부품명 STM32WB50CG
상세설명  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 or 802.15.4 radio solution
PDF  119 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STM32WB50CG 데이터시트(HTML) 98 Page - STMicroelectronics

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Electrical characteristics
STM32WB50CG STM32WB30CE
98/119
DS13047 Rev 5
tADCVREG_STUP
ADC voltage regulator
start-up time
--
-
20
µs
tCONV
Total conversion time
(including sampling time)
fADC = 32 MHz
Resolution = 12 bits
0.469
-
20.41
µs
Resolution = 12 bits
ts + 12.5 cycles for successive
approximations = 15 to 653
1/fADC
IDDA(ADC)
ADC consumption from
the VDDA supply
fs = 2.13 Msps
-
340
415
µA
fs = 1 Msps
-
160
220
fs = 10 ksps
-
16
50
IDDV_S(ADC)
ADC consumption from
the VREF+ single ended
mode
fs = 2.13 Msps
-
64
80
µA
fs = 1 Msps
-
30
40
fs = 10 ksps
-
0.6
2
IDDV_D(ADC)
ADC consumption from
the VREF+ differential
mode
fs = 2.13 Msps
-
128
155
µA
fs = 1 Msps
-
60
70
fs = 10 ksps
-
1.3
3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3.
VREF+ is internally connected to VDDA and VREF- is internally connected to VSS.
Table 70. ADC characteristics(1) (2) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 71. ADC sampling time(1)(2)
Resolution (bits)
RAIN
(kΩ)
Minimum sampling time (ns)
Sampling cycles
12
057
2.5
0.05
62
2.5
0.1
67
2.5
0.2
76
2.5
0.5
104
6.5
1151
6.5
5
526
24.5
10
994
47.5
20
1932
92.5
50
4744
247.5
100
9430
640.5



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