STM32WB50CG datasheet(31/119 Pages) STMICROELECTRONICS

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Standby

LPR

OFF

SRAM2a

ON(8)

LSE,

LSI

RF, BOR, RTC, IWDG

All other peripherals are

powered off.

I/O configuration can be floating,

pull-up or pull-down

RF, Reset pin

2 I/Os (WKUPx)(9)

BOR, RTC, IWDG

0.32 µA w/o RTC

0.60 µA w RTC

51 µs

OFF

0.11 µA w/o RTC

0.39 µA w RTC

Shutdown

OFF

LSE

RTC

All other peripherals are

powered off.

I/O configuration can be floating,

pull-up or pull-down(10)

2 I/Os (WKUPx)(9),

RTC

0.028 µA w/o RTC

0.315 µA w/ RTC

1. Typical current at VDD = 2.4 V, 25 °C. for STOPx, SHUTDOWN and Standby, else VDD = 3.3 V, 25 °C.

2. The Flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM.

3. The SRAM1 and SRAM2 clocks can be gated off independently.

4. HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem.

5. HSI16 (16 MHz) automatically used by some peripherals.

6. U(S)ART reception is functional in Stop mode, and generates a wakeup interrupt on Start, Address match or Received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. SRAM1 and SRAM2b are OFF.

9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PA2.

10. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode.

Table 6. STM32WB50CG and STM32WB30CE modes overview (continued)

Mode

Regulator

CPU1

Flash

SRAM

Clocks

DMA and peripherals

Wakeup source

Consumption(1)

Wakeup time

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