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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32WB50CG 데이터시트(PDF) 19 Page - STMicroelectronics |
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STM32WB50CG 데이터시트(HTML) 19 Page - STMicroelectronics |
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19 / 119 page  DS13047 Rev 5 19/119 STM32WB50CG STM32WB30CE Functional overview 45 Figure 3. STM32WB50CG and STM32WB30CE RF front-end block diagram 3.6.2 BLE general description The BLE block is a master/slave processor, compliant with Bluetooth specification 5.2 standard. It integrates a 2.4 GHz RF transceiver and a powerful Cortex®-M0+ core, on which a complete power-optimized stack for Bluetooth Low Energy protocol runs, providing master / slave role support GAP: central, peripheral, observer or broadcaster roles ATT/GATT: client and server SM: privacy, authentication and authorization L2CAP Link layer: AES-128 encryption and decryption MSv63013V2 Note: UFQFPN48: VSS through exposed pad, and VSSRF pin must be connected to ground plane BP filter PLL RF1 Adjust 32 MHz OSC_OUT OSC_IN BLE modulator BLE demodulator BLE controller 802.15.4 MAC 802.15.4 modulator 802.15.4 demodulator RF control AGC Timer and Power control LDO LDO LDO VDD Trimmed bias VDDRF Max PA level Adjust HSE G G LNA Wakeup Interrupt Wakeup Interrupt AHB APB APB See note |
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