XIO2000 datasheet(114/150 Pages) TI

114 / 150 page

PCI Express Extended Configuration Space

102

November 2005

SCPS097B

5.19 Port VC Control Register

The port VC control register allows software to configure the VC arbitration options within the bridge. See

Table 5−15 for a complete description of the register contents.

PCI Express extended register offset:

15Ch

Read-only, Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 5−15. Port VC Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:4

RSVD

Reserved. Returns 000h when read.

3:1

VC_ARB

_SELECT

VC arbitration select. This read/write field allows software to define the mechanism used for VC

arbitration by the bridge. The value written to this field indicates the bit position within bits 7:0

(VC_ARB_CAP) in the port VC capability register 2 (offset 158h, see Section 5.18) that corresponds

to the selected arbitration scheme. Values that may be written to this field include:

000 = Hardware-fixed round-robin (default)

001 = WRR with 32 phases

All other values are reserved for arbitrations schemes that are not supported by the bridge.

LOAD_VC

_TABLE

Load VC arbitration table. When software writes a 1b to this bit, the bridge applies the values written

in the VC arbitration table within the extended configuration space to the actual VC arbitration tables

used by the device for arbitration. This bit always returns 0b when read.

5.20 Port VC Status Register

The port VC status register allows software to monitor the status of the VC arbitration table. See Table 5−16

for a complete description of the register contents.

PCI Express extended register offset:

15Eh

Read-only

Default value:

0000h

BIT NUMBER

RESET STATE

Table 5−16. Port VC Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:1

RSVD

Reserved. Returns 000 0000 0000 0000b when read.

VC_TABLE_STATUS

VC arbitration table status. This bit is automatically set by hardware when any modification is

made to the VC arbitration table entries within the extended configuration space. This bit is

cleared by hardware after software has requested a VC arbitration table refresh and the

refresh has been completed.

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