MSP430 datasheet(4/88 Pages) TI

4 / 88 page

Table 5-1. Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NO.

SCLK

SPI serial clock. Data can be transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input.

Connect to GND or logic low if not used. Do not leave any digital input pins floating.

SCLR

DAC clear input pin in SPI mode. A logic high on this pin forces the DAC output into a CLEAR state.

Connect to GND in UBM. Do not leave any digital input pins floating.

SDI

SPI data input. Data are clocked into the 24

‑bit input shift register on the falling edge of the serial clock

input. SDI is a Schmitt-Trigger logic input. Do not leave any digital input pins floating.

SDO

SPI data output. Data are output on the rising edge of SCLK when CS is logic low. Interrupt request (IRQ)

pin in the UART break mode (UBM). The output is in a Hi-Z state at power up and must be enabled in the

CONFIG register.

UARTIN

UART data input. Connect to IOVDD or logic high if not used. Do not leave any digital input pins floating.

UARTOUT

UART data output. This pin can be configured to function as the IRQ pin in SPI only mode.

VDD

P/AO

Power supply. When 2.7 V to 5.5 V is provided on PVDD pin, the internal LDO drives VDD internally.

Connect a 1

‑μF to 10‑μF capacitor to this pin. When 1.71 V to 1.89 V is provided on the PVDD pin, an

external power supply must be provided on this pin.

VOUT

DAC output voltage.

VREFIO

AI/AO

When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this

case, a load capacitance of 70-nF to 130-nF is required for stability. When disabled, this pin is the

external 1.25

‑V reference input.

(1)

AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power.

AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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