MSP430 datasheet(59/88 Pages) TI

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7.6.1.11 TRIGGER Register (Offset = Ah) [Reset = 0000h]

Return to the Register Map.

Table 7-22. TRIGGER Register Field Descriptions

Bit

Field

Type

Reset

Description

15-2

RESERVED

SHADOWLOAD

WSC

Shadowload Trigger

This trigger initiates the loading of the OTP array into the parallel

latches. If an OTP CRC error is detected, assert this trigger to try and

reload the OTP into the memory locations.

ADC

WSC

ADC Trigger

In auto mode, this bit enables or disables the conversions. Manually

set 1 (enable) and 0 (disable). In direct mode, setting this bit starts a

conversion sequence. The bit is cleared at the end of the sequence.

To stop a sequence prematurely, manually clear this bit.

7.6.1.12 SPECIAL_CFG Register (Offset = Bh) [Reset = 0000h]

Return to the Register Map.

Table 7-23. SPECIAL_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

15-3

RESERVED

OTP_LOAD_SW_RST

R/W

OTP (One Time Programmable Factory Trimmed Registers) LOAD

with SW RESET

OTP reloads with the assertion of a software reset (SW_RST).

0h = No reload with SW_RST

1h = Reload with SW_RST

ALMV_POL

R/W

Alarm Voltage Polarity

This register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB

bit is low) to control the VOUT during a hardware reset condition

or if alarm is active and alarm action is set appropriately. The

following Boolean function is implemented for the internal signal

ALMV_POL_o that sets the VOUT voltage:

ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT

AIN1_ENB)

0h = Low (0 V)

1h = High (2.5 V)

AIN1_ENB

R/W

AIN1 Pin Enable

This bit determines whether the POL_SEL/AIN1 pin acts as alarm

voltage polarity control bit or an input channel to the ADC.

0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts

GND

1h = AIN1 pin is an active channel to the ADC

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AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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